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| author | Marc Zyngier <marc.zyngier@arm.com> | 2016-10-17 13:47:34 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2016-10-17 15:54:30 +0100 |
| commit | 850540351bb1a4fa5f192e5ce55b89928cc57f42 (patch) | |
| tree | 52f1d8b1618bdf86eef79f38137651c288180a2e /arch | |
| parent | 9a1a1f404be55b07aea64864f98d7306cc493360 (diff) | |
| download | linux-stable-850540351bb1a4fa5f192e5ce55b89928cc57f42.tar.gz linux-stable-850540351bb1a4fa5f192e5ce55b89928cc57f42.tar.bz2 linux-stable-850540351bb1a4fa5f192e5ce55b89928cc57f42.zip | |
arm64: kernel: Init MDCR_EL2 even in the absence of a PMU
Commit f436b2ac90a0 ("arm64: kernel: fix architected PMU registers
unconditional access") made sure we wouldn't access unimplemented
PMU registers, but also left MDCR_EL2 uninitialized in that case,
leading to trap bits being potentially left set.
Make sure we always write something in that register.
Fixes: f436b2ac90a0 ("arm64: kernel: fix architected PMU registers unconditional access")
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/kernel/head.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 427f6d3f084c..332e33193ccf 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -586,8 +586,9 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems b.lt 4f // Skip if no PMU present mrs x0, pmcr_el0 // Disable debug access traps ubfx x0, x0, #11, #5 // to EL2 and allow access to - msr mdcr_el2, x0 // all PMU counters from EL1 4: + csel x0, xzr, x0, lt // all PMU counters from EL1 + msr mdcr_el2, x0 // (if they exist) /* Stage-2 translation */ msr vttbr_el2, xzr |