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| author | Mark Rutland <mark.rutland@arm.com> | 2016-08-24 18:02:08 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-09-07 08:34:49 +0200 |
| commit | bf436012e7195f16b8a0e2626560869c8bc6c2a1 (patch) | |
| tree | 14e156a62545697f2802b0b43f55ac2d4b4a3a90 /arch | |
| parent | 6cdff5a9d1be0aaac57a9026790383a947291162 (diff) | |
| download | linux-stable-bf436012e7195f16b8a0e2626560869c8bc6c2a1.tar.gz linux-stable-bf436012e7195f16b8a0e2626560869c8bc6c2a1.tar.bz2 linux-stable-bf436012e7195f16b8a0e2626560869c8bc6c2a1.zip | |
arm64: avoid TLB conflict with CONFIG_RANDOMIZE_BASE
commit fd363bd417ddb6103564c69cfcbd92d9a7877431 upstream.
When CONFIG_RANDOMIZE_BASE is selected, we modify the page tables to remap the
kernel at a newly-chosen VA range. We do this with the MMU disabled, but do not
invalidate TLBs prior to re-enabling the MMU with the new tables. Thus the old
mappings entries may still live in TLBs, and we risk violating
Break-Before-Make requirements, leading to TLB conflicts and/or other issues.
We invalidate TLBs when we uninsall the idmap in early setup code, but prior to
this we are subject to issues relating to the Break-Before-Make violation.
Avoid these issues by invalidating the TLBs before the new mappings can be
used by the hardware.
Fixes: f80fb3a3d508 ("arm64: add support for kernel ASLR")
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/kernel/head.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 2c6e598a94dc..aa68aadcdeea 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -757,6 +757,9 @@ ENTRY(__enable_mmu) isb bl __create_page_tables // recreate kernel mapping + tlbi vmalle1 // Remove any stale TLB entries + dsb nsh + msr sctlr_el1, x19 // re-enable the MMU isb ic iallu // flush instructions fetched |