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| author | Marc Zyngier <marc.zyngier@arm.com> | 2016-10-17 13:47:34 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-10-28 03:45:29 -0400 |
| commit | 32c0a66fad76d8dc6b83ed53db3c336d0a1706b9 (patch) | |
| tree | ff5ad1e512c401891c0acde9db6f9c8fabffd242 /arch | |
| parent | 69e1b2d4399c39f4df4742be2b7675805bd56714 (diff) | |
| download | linux-stable-32c0a66fad76d8dc6b83ed53db3c336d0a1706b9.tar.gz linux-stable-32c0a66fad76d8dc6b83ed53db3c336d0a1706b9.tar.bz2 linux-stable-32c0a66fad76d8dc6b83ed53db3c336d0a1706b9.zip | |
arm64: kernel: Init MDCR_EL2 even in the absence of a PMU
commit 850540351bb1a4fa5f192e5ce55b89928cc57f42 upstream.
Commit f436b2ac90a0 ("arm64: kernel: fix architected PMU registers
unconditional access") made sure we wouldn't access unimplemented
PMU registers, but also left MDCR_EL2 uninitialized in that case,
leading to trap bits being potentially left set.
Make sure we always write something in that register.
Fixes: f436b2ac90a0 ("arm64: kernel: fix architected PMU registers unconditional access")
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/kernel/head.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 3e7b050e99dc..4d19508c55a3 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -578,8 +578,9 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems b.lt 4f // Skip if no PMU present mrs x0, pmcr_el0 // Disable debug access traps ubfx x0, x0, #11, #5 // to EL2 and allow access to - msr mdcr_el2, x0 // all PMU counters from EL1 4: + csel x0, xzr, x0, lt // all PMU counters from EL1 + msr mdcr_el2, x0 // (if they exist) /* Stage-2 translation */ msr vttbr_el2, xzr |