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author | Patrick Stählin <me@packi.ch> | 2018-11-09 22:42:16 +0100 |
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committer | Palmer Dabbelt <palmer@sifive.com> | 2018-11-20 05:19:28 -0800 |
commit | 5d8f81ba1da55210123b9595e87b913c79579d02 (patch) | |
tree | ab18ae8ecb86c0df3a2419132b3afb7ee393f0b9 /arch | |
parent | 27f8899d6002e11a6e2d995e29b8deab5aa9cc25 (diff) | |
download | linux-stable-5d8f81ba1da55210123b9595e87b913c79579d02.tar.gz linux-stable-5d8f81ba1da55210123b9595e87b913c79579d02.tar.bz2 linux-stable-5d8f81ba1da55210123b9595e87b913c79579d02.zip |
RISC-V: recognize S/U mode bits in print_isa
Removes the warning about an unsupported ISA when reading /proc/cpuinfo
on QEMU. The "S" extension is not being returned as it is not accessible
from userspace.
Signed-off-by: Patrick Stählin <me@packi.ch>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/riscv/kernel/cpu.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3a5a2ee31547..b4a7d4427fbb 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node) static void print_isa(struct seq_file *f, const char *orig_isa) { - static const char *ext = "mafdc"; + static const char *ext = "mafdcsu"; const char *isa = orig_isa; const char *e; @@ -88,11 +88,14 @@ static void print_isa(struct seq_file *f, const char *orig_isa) /* * Check the rest of the ISA string for valid extensions, printing those * we find. RISC-V ISA strings define an order, so we only print the - * extension bits when they're in order. + * extension bits when they're in order. Hide the supervisor (S) + * extension from userspace as it's not accessible from there. */ for (e = ext; *e != '\0'; ++e) { if (isa[0] == e[0]) { - seq_write(f, isa, 1); + if (isa[0] != 's') + seq_write(f, isa, 1); + isa++; } } |