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| author | Tony Lindgren <tony@atomide.com> | 2019-12-12 09:46:12 -0800 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2020-01-23 08:24:46 -0800 |
| commit | 316a418e28b6a4c72b991eebdd191c44ad5c2215 (patch) | |
| tree | ffc52486493be1d13a6aa355078b28cfbdeb9dad /arch | |
| parent | 18c48e6d5bb21558ea7f9bcc8e263b83fbad127a (diff) | |
| download | linux-stable-316a418e28b6a4c72b991eebdd191c44ad5c2215.tar.gz linux-stable-316a418e28b6a4c72b991eebdd191c44ad5c2215.tar.bz2 linux-stable-316a418e28b6a4c72b991eebdd191c44ad5c2215.zip | |
ARM: dts: Configure interconnect target module for omap4 aes
We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/omap4.dtsi | 66 |
1 files changed, 54 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index e3c0732a1a3f..40212fa6a8cf 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -266,22 +266,64 @@ hw-caps-temp-alert; }; - aes1: aes@4b501000 { - compatible = "ti,omap4-aes"; + aes1_target: target-module@4b501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "aes1"; - reg = <0x4b501000 0xa0>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 111>, <&sdma 110>; - dma-names = "tx", "rx"; + reg = <0x4b501080 0x4>, + <0x4b501084 0x4>, + <0x4b501088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b501000 0x1000>; + + aes1: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 111>, <&sdma 110>; + dma-names = "tx", "rx"; + }; }; - aes2: aes@4b701000 { - compatible = "ti,omap4-aes"; + aes2_target: target-module@4b701000 { + compatible = "ti,sysc-omap2", "ti,sysc"; ti,hwmods = "aes2"; - reg = <0x4b701000 0xa0>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&sdma 114>, <&sdma 113>; - dma-names = "tx", "rx"; + reg = <0x4b701080 0x4>, + <0x4b701084 0x4>, + <0x4b701088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */ + clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b701000 0x1000>; + + aes2: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; }; des: des@480a5000 { |