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author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2018-08-22 21:13:02 +0900 |
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committer | Tejun Heo <tj@kernel.org> | 2018-08-22 08:08:27 -0700 |
commit | 9d2ab99573970838108add835442a03e23f8577b (patch) | |
tree | bb6c8eb9824775a21c550fe24a8f5d03c83b5cb4 /drivers/ata/ahci.h | |
parent | 16af2d65842d343c2f95733c3993a0b5baab08f9 (diff) | |
download | linux-stable-9d2ab99573970838108add835442a03e23f8577b.tar.gz linux-stable-9d2ab99573970838108add835442a03e23f8577b.tar.bz2 linux-stable-9d2ab99573970838108add835442a03e23f8577b.zip |
ata: libahci_platform: add reset control support
Add support to get and control a list of resets for the device
as optional and shared. These resets must be kept de-asserted until
the device is enabled.
This is specified as shared because some SoCs like UniPhier series
have common reset controls with all ahci controller instances.
However, according to Thierry's view,
https://www.spinics.net/lists/linux-ide/msg55357.html
some hardware-specific drivers already use their own resets,
and the common reset make a path to occur double controls of resets.
The ahci_platform_get_resources() can get and control the reset
only when the second argument includes AHCI_PLATFORM_GET_RESETS bit.
Suggested-by: Hans de Goede <hdegoede@redhat.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/ata/ahci.h')
-rw-r--r-- | drivers/ata/ahci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index 1609ebab4e23..6a1515f0da40 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -350,6 +350,7 @@ struct ahci_host_priv { u32 em_msg_type; /* EM message type */ bool got_runtime_pm; /* Did we do pm_runtime_get? */ struct clk *clks[AHCI_MAX_CLKS]; /* Optional */ + struct reset_control *rsts; /* Optional */ struct regulator **target_pwrs; /* Optional */ /* * If platform uses PHYs. There is a 1:1 relation between the port number and |