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| author | Suman Tripathi <stripathi@apm.com> | 2014-07-29 12:24:49 +0530 |
|---|---|---|
| committer | Tejun Heo <tj@kernel.org> | 2014-07-29 10:25:57 -0400 |
| commit | aeae4dcac5a91de9546c42a3be09c96479bfc3ff (patch) | |
| tree | 195b7d53738841e0f7a7bb8079093263629efd58 /drivers/ata/ahci_xgene.c | |
| parent | 09de99db23df55c7415d110f6c62281dedd77384 (diff) | |
| download | linux-stable-aeae4dcac5a91de9546c42a3be09c96479bfc3ff.tar.gz linux-stable-aeae4dcac5a91de9546c42a3be09c96479bfc3ff.tar.bz2 linux-stable-aeae4dcac5a91de9546c42a3be09c96479bfc3ff.zip | |
ahci_xgene: Fix the watermark threshold for the APM X-Gene SATA host controller driver.
As per SATA IO specification, when Host sends HOLD, the device takes
about 20DW latency to reply to HOLDA. In some case, device doesn't
response to HOLDA over 20DW and causes FIFO goes into over flow
condition. Due to this condition, device enumerations fails with
those devices. This patch adjust the watermark FIFO by increasing
the FIFO depth from 0x16(default) to 0x30 to address this issue.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/ata/ahci_xgene.c')
| -rw-r--r-- | drivers/ata/ahci_xgene.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c index a9fc2ae2e6e2..3db8eaae1576 100644 --- a/drivers/ata/ahci_xgene.c +++ b/drivers/ata/ahci_xgene.c @@ -67,6 +67,9 @@ #define PORTAXICFG 0x000000bc #define PORTAXICFG_OUTTRANS_SET(dst, src) \ (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000)) +#define PORTRANSCFG 0x000000c8 +#define PORTRANSCFG_RXWM_SET(dst, src) \ + (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f)) /* SATA host controller AXI CSR */ #define INT_SLV_TMOMASK 0x00000010 @@ -176,6 +179,10 @@ static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel) val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */ writel(val, mmio + PORTAXICFG); readl(mmio + PORTAXICFG); /* Force a barrier */ + /* Set the watermark threshold of the receive FIFO */ + val = readl(mmio + PORTRANSCFG); + val = PORTRANSCFG_RXWM_SET(val, 0x30); + writel(val, mmio + PORTRANSCFG); } /** |