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author | Arnd Bergmann <arnd@arndb.de> | 2019-02-15 17:17:33 +0100 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2019-02-15 17:17:57 +0100 |
commit | c9235d9996463ba8e8dde7bfe659352b20739e36 (patch) | |
tree | 4dc60542d0c356b2138f0ee8a8fdffa7c84a2e7d /drivers/bus | |
parent | 59f527dd7a6191734f7c2049f045cbcac290efa8 (diff) | |
parent | d90bf296ae18f26a18e572965fc0047fa1bd37a8 (diff) | |
download | linux-stable-c9235d9996463ba8e8dde7bfe659352b20739e36.tar.gz linux-stable-c9235d9996463ba8e8dde7bfe659352b20739e36.tar.bz2 linux-stable-c9235d9996463ba8e8dde7bfe659352b20739e36.zip |
Merge tag 'imx-drivers-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.1:
- Do not get GPCv2 driver depend on SOC_IMX8MQ since the driver is
going to be used on more SoCs than just i.MX8MQ.
- Add power domain information into SCU bindings document.
- Add support of start/stop a CPU into imx firmware driver.
- Support multiple address ranges per child node for imx-weim bus
driver.
* tag 'imx-drivers-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
firmware: imx: Add support to start/stop a CPU
soc: imx: Break dependency on SOC_IMX8MQ for GPCv2
firmware: imx: scu-pd: add fallback compatible string support
dt-bindings: fsl: scu: add imx8qm scu power domain support
dt-bindings: fsl: scu: add fallback compatible string for power domain
bus: imx-weim: guard against timing configuration conflicts
bus: imx-weim: support multiple address ranges per child node
dt-bindings: bus: imx-weim: document multiple address ranges per child node
soc: imx: gpcv2: handle reset clocks
soc: imx: gpcv2: handle additional power-down bits in handshake register
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/bus')
-rw-r--r-- | drivers/bus/imx-weim.c | 70 |
1 files changed, 57 insertions, 13 deletions
diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index d84996a4528e..db74334ca5ef 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -46,6 +46,17 @@ static const struct imx_weim_devtype imx51_weim_devtype = { }; #define MAX_CS_REGS_COUNT 6 +#define MAX_CS_COUNT 6 +#define OF_REG_SIZE 3 + +struct cs_timing { + bool is_applied; + u32 regs[MAX_CS_REGS_COUNT]; +}; + +struct cs_timing_state { + struct cs_timing cs[MAX_CS_COUNT]; +}; static const struct of_device_id weim_id_table[] = { /* i.MX1/21 */ @@ -111,21 +122,19 @@ err: } /* Parse and set the timing for this device. */ -static int __init weim_timing_setup(struct device_node *np, void __iomem *base, - const struct imx_weim_devtype *devtype) +static int __init weim_timing_setup(struct device *dev, + struct device_node *np, void __iomem *base, + const struct imx_weim_devtype *devtype, + struct cs_timing_state *ts) { u32 cs_idx, value[MAX_CS_REGS_COUNT]; int i, ret; + int reg_idx, num_regs; + struct cs_timing *cst; if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT)) return -EINVAL; - - /* get the CS index from this child node's "reg" property. */ - ret = of_property_read_u32(np, "reg", &cs_idx); - if (ret) - return ret; - - if (cs_idx >= devtype->cs_count) + if (WARN_ON(devtype->cs_count > MAX_CS_COUNT)) return -EINVAL; ret = of_property_read_u32_array(np, "fsl,weim-cs-timing", @@ -133,9 +142,43 @@ static int __init weim_timing_setup(struct device_node *np, void __iomem *base, if (ret) return ret; - /* set the timing for WEIM */ - for (i = 0; i < devtype->cs_regs_count; i++) - writel(value[i], base + cs_idx * devtype->cs_stride + i * 4); + /* + * the child node's "reg" property may contain multiple address ranges, + * extract the chip select for each. + */ + num_regs = of_property_count_elems_of_size(np, "reg", OF_REG_SIZE); + if (num_regs < 0) + return num_regs; + if (!num_regs) + return -EINVAL; + for (reg_idx = 0; reg_idx < num_regs; reg_idx++) { + /* get the CS index from this child node's "reg" property. */ + ret = of_property_read_u32_index(np, "reg", + reg_idx * OF_REG_SIZE, &cs_idx); + if (ret) + break; + + if (cs_idx >= devtype->cs_count) + return -EINVAL; + + /* prevent re-configuring a CS that's already been configured */ + cst = &ts->cs[cs_idx]; + if (cst->is_applied && memcmp(value, cst->regs, + devtype->cs_regs_count * sizeof(u32))) { + dev_err(dev, "fsl,weim-cs-timing conflict on %pOF", np); + return -EINVAL; + } + + /* set the timing for WEIM */ + for (i = 0; i < devtype->cs_regs_count; i++) + writel(value[i], + base + cs_idx * devtype->cs_stride + i * 4); + if (!cst->is_applied) { + cst->is_applied = true; + memcpy(cst->regs, value, + devtype->cs_regs_count * sizeof(u32)); + } + } return 0; } @@ -148,6 +191,7 @@ static int __init weim_parse_dt(struct platform_device *pdev, const struct imx_weim_devtype *devtype = of_id->data; struct device_node *child; int ret, have_child = 0; + struct cs_timing_state ts = {}; if (devtype == &imx50_weim_devtype) { ret = imx_weim_gpr_setup(pdev); @@ -156,7 +200,7 @@ static int __init weim_parse_dt(struct platform_device *pdev, } for_each_available_child_of_node(pdev->dev.of_node, child) { - ret = weim_timing_setup(child, base, devtype); + ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts); if (ret) dev_warn(&pdev->dev, "%pOF set timing failed.\n", child); |