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| author | Jiancheng Xue <xuejiancheng@hisilicon.com> | 2016-04-23 15:40:28 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-05-06 11:13:29 -0700 |
| commit | 25824d52caa8e614b695a7197a8edde19f5b02ad (patch) | |
| tree | 5f183fec712cdf5802e858d4112483eaf98f6ec8 /drivers/clk/hisilicon/Kconfig | |
| parent | f55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff) | |
| download | linux-stable-25824d52caa8e614b695a7197a8edde19f5b02ad.tar.gz linux-stable-25824d52caa8e614b695a7197a8edde19f5b02ad.tar.bz2 linux-stable-25824d52caa8e614b695a7197a8edde19f5b02ad.zip | |
reset: hisilicon: add reset controller driver for hisilicon SOCs
In most of hisilicon SOCs, reset controller and clock provider are
combined together as a block named CRG (Clock and Reset Generator).
This patch mainly implements the reset function.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/hisilicon/Kconfig')
| -rw-r--r-- | drivers/clk/hisilicon/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index e43485448612..3cd349c728e9 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -5,6 +5,13 @@ config COMMON_CLK_HI6220 help Build the Hisilicon Hi6220 clock driver based on the common clock framework. +config RESET_HISI + bool "HiSilicon Reset Controller Driver" + depends on ARCH_HISI || COMPILE_TEST + select RESET_CONTROLLER + help + Build reset controller driver for HiSilicon device chipsets. + config STUB_CLK_HI6220 bool "Hi6220 Stub Clock Driver" depends on COMMON_CLK_HI6220 && MAILBOX |