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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-07-11 13:14:44 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-08-27 17:00:18 +0200 |
| commit | 38c79e2899a66096583f3377c64b35f30584f1b4 (patch) | |
| tree | 7c8242b3318f184e721cb57cfdc6d6e5f5c05467 /drivers/clk/renesas/rcar-gen3-cpg.c | |
| parent | fdb78a8c35bce065272d71ac7eb64d6d7512db99 (diff) | |
| download | linux-stable-38c79e2899a66096583f3377c64b35f30584f1b4.tar.gz linux-stable-38c79e2899a66096583f3377c64b35f30584f1b4.tar.bz2 linux-stable-38c79e2899a66096583f3377c64b35f30584f1b4.zip | |
clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider
Add a clock type and macro for defining clocks using the OSC EXTAL
predivider combined with a fixed divider.
On most R-Car Gen3 SoCs, the predivider value depends on mode pins, and
thus must be specified in the configuration structure.
Inspired by a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.c')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 628b63b85d3f..7533a51c679b 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -563,6 +563,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, return cpg_z_clk_register(core->name, __clk_get_name(parent), base, CPG_FRQCRC_Z2FC_MASK); + case CLK_TYPE_GEN3_OSC: + /* + * Clock combining OSC EXTAL predivider and a fixed divider + */ + div = cpg_pll_config->osc_prediv * core->div; + break; + default: return ERR_PTR(-EINVAL); } |