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author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-07-19 17:39:54 +0200 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-08-16 09:51:47 +0200 |
commit | 696997e004d4179f462d2ebd3efeb12a7cec5ef7 (patch) | |
tree | 61f14f2eafb16020aac087c1e5354980eec1aea8 /drivers/clk/renesas/rcar-gen3-cpg.c | |
parent | 09a7dea9d58aadda90af5ad4dce1d540fe830868 (diff) | |
download | linux-stable-696997e004d4179f462d2ebd3efeb12a7cec5ef7.tar.gz linux-stable-696997e004d4179f462d2ebd3efeb12a7cec5ef7.tar.bz2 linux-stable-696997e004d4179f462d2ebd3efeb12a7cec5ef7.zip |
clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car
D3), a peripheral clock divider has been added, to select between clean
and spread spectrum parents.
Add a new clock type to the R-Car Gen3 driver core to handle this.
To avoid increasing the size of struct cpg_core_clk, both parents and
dividers are stored in the existing parent resp. div fields.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.c')
-rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 3f922fea9671..951105816547 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -272,7 +272,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, unsigned int div = 1; u32 value; - parent = clks[core->parent]; + parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */ if (IS_ERR(parent)) return ERR_CAST(parent); @@ -355,6 +355,24 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, parent = clks[cpg_clk_extalr]; break; + case CLK_TYPE_GEN3_PE: + /* + * Peripheral clock with a fixed divider, selectable between + * clean and spread spectrum parents using MD12 + */ + if (cpg_mode & BIT(12)) { + /* Clean */ + div = core->div & 0xffff; + } else { + /* SCCG */ + parent = clks[core->parent >> 16]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + div = core->div >> 16; + } + mult = 1; + break; + default: return ERR_PTR(-EINVAL); } |