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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-07-11 14:19:47 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-08-27 17:00:18 +0200 |
| commit | cd51e427e050f6a3d3bc3e0e38ad30974a52cb44 (patch) | |
| tree | a7fbed62d86fd387961b73a02ff2640cd127d869 /drivers/clk/renesas/rcar-gen3-cpg.c | |
| parent | 4f57998d647772280a6442bbc746249e5bfee572 (diff) | |
| download | linux-stable-cd51e427e050f6a3d3bc3e0e38ad30974a52cb44.tar.gz linux-stable-cd51e427e050f6a3d3bc3e0e38ad30974a52cb44.tar.bz2 linux-stable-cd51e427e050f6a3d3bc3e0e38ad30974a52cb44.zip | |
clk: renesas: rcar-gen3: Add support for mode pin clock selection
Make the existing support for selecting between clean and SSCG clocks
using MD12 more generic, to allow using other mode pins for arbitrary
clock selection.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.c')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 19a77822757d..4346fdeef01b 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -539,16 +539,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, parent = clks[cpg_clk_extalr]; break; - case CLK_TYPE_GEN3_PE: + case CLK_TYPE_GEN3_MDSEL: /* - * Peripheral clock with a fixed divider, selectable between - * clean and spread spectrum parents using MD12 + * Clock selectable between two parents and two fixed dividers + * using a mode pin */ - if (cpg_mode & BIT(12)) { - /* Clean */ + if (cpg_mode & BIT(core->offset)) { div = core->div & 0xffff; } else { - /* SCCG */ parent = clks[core->parent >> 16]; if (IS_ERR(parent)) return ERR_CAST(parent); |