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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-01-21 14:07:39 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-01-24 16:01:08 +0100 |
| commit | d9286d9743b6e8cfbf1a13f8db84e9c65c0b09c7 (patch) | |
| tree | 4b69ea99bb916242930a53667951e13ccad64f57 /drivers/clk/renesas/rcar-gen3-cpg.c | |
| parent | 9d034e151b407cbd2c66bc4c48b423f814533374 (diff) | |
| download | linux-stable-d9286d9743b6e8cfbf1a13f8db84e9c65c0b09c7.tar.gz linux-stable-d9286d9743b6e8cfbf1a13f8db84e9c65c0b09c7.tar.bz2 linux-stable-d9286d9743b6e8cfbf1a13f8db84e9c65c0b09c7.zip | |
clk: renesas: r8a774c0: Correct parent clock of DU
According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
the parent clock of the DU module clocks on RZ/G2E is S1D1.
Fixes: 906e0a4a6d1ef2d3 ("clk: renesas: cpg-mssr: Add r8a774c0 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.c')
0 files changed, 0 insertions, 0 deletions