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author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-05-04 14:32:56 +0200 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-06-06 11:58:31 +0200 |
commit | 5b1defde7054e66da5c0f6cba8b35cef29edede0 (patch) | |
tree | c3f4f475b8f73ebeea57b8a334a32f54b56285f5 /drivers/clk/renesas/rcar-gen3-cpg.h | |
parent | 972610fb23b08dd54879102a9d5be695d53b728b (diff) | |
download | linux-stable-5b1defde7054e66da5c0f6cba8b35cef29edede0.tar.gz linux-stable-5b1defde7054e66da5c0f6cba8b35cef29edede0.tar.bz2 linux-stable-5b1defde7054e66da5c0f6cba8b35cef29edede0.zip |
clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code
Extract the code to support parts common to all members of the R-Car
Gen3 SoC family into a separate file, to ease sharing among SoC-specific
drivers.
Note that while the cpg_pll_configs[] arrays and the selection of the
config based on the MODE bits are identical on R-Car H3 and R-Car M3-W,
they are not common, and may be different on other R-Car Gen3 SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.h')
-rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h new file mode 100644 index 000000000000..f699085147d1 --- /dev/null +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -0,0 +1,43 @@ +/* + * R-Car Gen3 Clock Pulse Generator + * + * Copyright (C) 2015-2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ +#define __CLK_RENESAS_RCAR_GEN3_CPG_H__ + +enum rcar_gen3_clk_types { + CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, + CLK_TYPE_GEN3_PLL0, + CLK_TYPE_GEN3_PLL1, + CLK_TYPE_GEN3_PLL2, + CLK_TYPE_GEN3_PLL3, + CLK_TYPE_GEN3_PLL4, + CLK_TYPE_GEN3_SD, + CLK_TYPE_GEN3_R, +}; + +#define DEF_GEN3_SD(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) + +struct rcar_gen3_cpg_pll_config { + unsigned int extal_div; + unsigned int pll1_mult; + unsigned int pll3_mult; +}; + +#define CPG_RCKCR 0x240 + +u32 rcar_gen3_read_mode_pins(void); +struct clk *rcar_gen3_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, + struct clk **clks, void __iomem *base); +int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, + unsigned int clk_extalr); + +#endif |