diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2019-01-22 22:59:35 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-02-05 10:40:05 +0100 |
| commit | db4a0073cc82a95d8d1a9b05fde82355fcce77d8 (patch) | |
| tree | 1665ec55ec174a7d075fd77da2132efad343f435 /drivers/clk/renesas/rcar-gen3-cpg.h | |
| parent | 875e8f6b0156c0ad56fd0c29c78e3f2f67ec0b16 (diff) | |
| download | linux-stable-db4a0073cc82a95d8d1a9b05fde82355fcce77d8.tar.gz linux-stable-db4a0073cc82a95d8d1a9b05fde82355fcce77d8.tar.bz2 linux-stable-db4a0073cc82a95d8d1a9b05fde82355fcce77d8.zip | |
clk: renesas: rcar-gen3: Add RPC clocks
The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
is different between SoCs; it makes sense to support the most common case
of this encoding in the R-Car gen3 CPG driver...
After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from
it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except
V3M (R8A77970); the composite clock driver seems handy for this task, using
the spinlock added in the previous patch...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index f4fb6cf16688..eac1b057455a 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -23,6 +23,9 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_Z2, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ + CLK_TYPE_GEN3_RPCSRC, + CLK_TYPE_GEN3_RPC, + CLK_TYPE_GEN3_RPCD2, /* SoC specific definitions start here */ CLK_TYPE_GEN3_SOC_BASE, @@ -57,6 +60,7 @@ struct rcar_gen3_cpg_pll_config { u8 osc_prediv; }; +#define CPG_RPCCKCR 0x238 #define CPG_RCKCR 0x240 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, |