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| author | Krzysztof Kozlowski <k.kozlowski@samsung.com> | 2016-05-11 14:02:11 +0200 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2016-06-02 11:18:11 +0200 |
| commit | 402b7cebf286d5c06c847c175ccc8405aabdae61 (patch) | |
| tree | 3d7c49e877b512c6a132e1d02e95c97d3cb41172 /drivers/clk/samsung | |
| parent | a6cd1fbc4b9d96becf7aa884f98e8a260da5301c (diff) | |
| download | linux-stable-402b7cebf286d5c06c847c175ccc8405aabdae61.tar.gz linux-stable-402b7cebf286d5c06c847c175ccc8405aabdae61.tar.bz2 linux-stable-402b7cebf286d5c06c847c175ccc8405aabdae61.zip | |
clk: samsung: exynos5433: Move PLL rates data to init section
The arrays with initialization data of PLLs can be moved to initconst
section because they are referenced only from other initconst-level
symbols.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index f202a51ff99b..5993bd5ac6ba 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -693,7 +693,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL */ -static const struct samsung_pll_rate_table exynos5443_pll_rates[] = { +static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = { PLL_35XX_RATE(2500000000U, 625, 6, 0), PLL_35XX_RATE(2400000000U, 500, 5, 0), PLL_35XX_RATE(2300000000U, 575, 6, 0), @@ -744,7 +744,7 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] = { }; /* AUD_PLL */ -static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { +static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] __initconst = { PLL_36XX_RATE(400000000U, 200, 3, 2, 0), PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), PLL_36XX_RATE(384000000U, 128, 2, 2, 0), |