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authorGeert Uytterhoeven <geert+renesas@glider.be>2014-11-24 15:57:59 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2015-01-08 16:13:19 +0100
commit7980a86190ffa006094c89941aebfdf8c62562da (patch)
treed84b7ed486f0922e2119c2605540f43c09f5d56e /drivers/clk/shmobile
parent97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff)
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clk: shmobile: div6: Avoid changing divisor in .disable()
While DIV6 clocks require the divisor field to be non-zero when stopping the clock, some clocks (e.g. ZB on sh73a0) fail to be re-enabled later if the divisor field is changed when stopping the clock. The reason for this is unknown. To fix this, do not touch the divisor field if it's already non-zero. On kzm9g, the smsc911x Ethernet controller is connected to the sh73a0 Bus State Controller, which is clocked by the ZB clock. Without this fix, if the ZB clock is disabled during system suspend, and re-enabled during resume, the kernel locks up when the smsc911x driver tries to access the Ethernet registers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Diffstat (limited to 'drivers/clk/shmobile')
-rw-r--r--drivers/clk/shmobile/clk-div6.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c
index 639241e31e03..efbaf6c81b75 100644
--- a/drivers/clk/shmobile/clk-div6.c
+++ b/drivers/clk/shmobile/clk-div6.c
@@ -54,12 +54,19 @@ static int cpg_div6_clock_enable(struct clk_hw *hw)
static void cpg_div6_clock_disable(struct clk_hw *hw)
{
struct div6_clock *clock = to_div6_clock(hw);
+ u32 val;
- /* DIV6 clocks require the divisor field to be non-zero when stopping
- * the clock.
+ val = clk_readl(clock->reg);
+ val |= CPG_DIV6_CKSTP;
+ /*
+ * DIV6 clocks require the divisor field to be non-zero when stopping
+ * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
+ * re-enabled later if the divisor field is changed when stopping the
+ * clock
*/
- clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK,
- clock->reg);
+ if (!(val & CPG_DIV6_DIV_MASK))
+ val |= CPG_DIV6_DIV_MASK;
+ clk_writel(val, clock->reg);
}
static int cpg_div6_clock_is_enabled(struct clk_hw *hw)