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authorStephen Boyd <sboyd@codeaurora.org>2017-04-07 12:21:33 -0700
committerMichael Turquette <mturquette@baylibre.com>2017-04-12 18:51:34 +0200
commit15a2a14b23024ab79fd22de28ba7c006be46aa53 (patch)
treec2a16722a237823238146c9fd9105e1708d3cf77 /drivers/clk/zte
parenta90099da3cd0921e853f7b7e0c74f140a78baeed (diff)
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clk: zte: Mark pll config tables as const
These should be const. Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk/zte')
-rw-r--r--drivers/clk/zte/clk-zx296718.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index 8db0119bc6f7..a10962988ba8 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -94,14 +94,14 @@
static DEFINE_SPINLOCK(clk_lock);
-static struct zx_pll_config pll_cpu_table[] = {
+static const struct zx_pll_config pll_cpu_table[] = {
PLL_RATE(1312000000, 0x00103621, 0x04aaaaaa),
PLL_RATE(1407000000, 0x00103a21, 0x04aaaaaa),
PLL_RATE(1503000000, 0x00103e21, 0x04aaaaaa),
PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa),
};
-static struct zx_pll_config pll_vga_table[] = {
+static const struct zx_pll_config pll_vga_table[] = {
PLL_RATE(36000000, 0x00102464, 0x04000000), /* 800x600@56 */
PLL_RATE(40000000, 0x00102864, 0x04000000), /* 800x600@60 */
PLL_RATE(49500000, 0x00103164, 0x04800000), /* 800x600@75 */