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| author | Rhyland Klein <rklein@nvidia.com> | 2016-01-14 14:24:35 -0500 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-02-02 15:49:24 +0100 |
| commit | 3dad5c5fa1d24c3bbb3e9e8ac0c52f35e045b807 (patch) | |
| tree | d3b7c9b1ec316b1bc5838f754c43f8b8a3250049 /drivers/clk | |
| parent | 3eb61566a6efc5a56ebe1e6b86519bc5e0b39003 (diff) | |
| download | linux-stable-3dad5c5fa1d24c3bbb3e9e8ac0c52f35e045b807.tar.gz linux-stable-3dad5c5fa1d24c3bbb3e9e8ac0c52f35e045b807.tar.bz2 linux-stable-3dad5c5fa1d24c3bbb3e9e8ac0c52f35e045b807.zip | |
clk: tegra: Fix pllx dyn step calculation
The logic for calculating the input rate used when figuring out the
proper dynamic steps for pllx was incorrect. It is supposed to be
calculated using parent_rate / m but it was just using the parent rate
directly, therefore using the wrong step values.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index caae0dcc9cb5..ffcb86a667d9 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -780,13 +780,13 @@ static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b) { unsigned long input_rate; - if (!IS_ERR_OR_NULL(hw->clk)) { + /* cf rate */ + if (!IS_ERR_OR_NULL(hw->clk)) input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); - /* cf rate */ - input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); - } else { + else input_rate = 38400000; - } + + input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); switch (input_rate) { case 12000000: |