diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2019-08-14 10:30:14 -0500 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-08-29 08:28:49 +0200 |
| commit | a8f7703f221347b7dcfa1d4077695782edddbf78 (patch) | |
| tree | b4c683b08e763390a0830d8485c08d2e56c0e695 /drivers/clk | |
| parent | b608a5a238d52d89e0b60a87400d3166f937c010 (diff) | |
| download | linux-stable-a8f7703f221347b7dcfa1d4077695782edddbf78.tar.gz linux-stable-a8f7703f221347b7dcfa1d4077695782edddbf78.tar.bz2 linux-stable-a8f7703f221347b7dcfa1d4077695782edddbf78.zip | |
clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
commit c7ec75ea4d5316518adc87224e3cff47192579e7 upstream.
Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/socfpga/clk-periph-s10.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c index 568f59b58ddf..e7c877d354c7 100644 --- a/drivers/clk/socfpga/clk-periph-s10.c +++ b/drivers/clk/socfpga/clk-periph-s10.c @@ -37,7 +37,7 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk, if (socfpgaclk->fixed_div) { div = socfpgaclk->fixed_div; } else { - if (!socfpgaclk->bypass_reg) + if (socfpgaclk->hw.reg) div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); } |