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author | Jon Hunter <jonathanh@nvidia.com> | 2019-06-05 15:01:39 +0100 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-09-16 08:22:16 +0200 |
commit | fa717fc442ff8098205b7bd86a5a26265fa8c9b9 (patch) | |
tree | 78aa84c61c1e7fb158b042d67eadeff35f05a33c /drivers/clk | |
parent | 350503c8982b7e518a136a816f292467deae7afe (diff) | |
download | linux-stable-fa717fc442ff8098205b7bd86a5a26265fa8c9b9.tar.gz linux-stable-fa717fc442ff8098205b7bd86a5a26265fa8c9b9.tar.bz2 linux-stable-fa717fc442ff8098205b7bd86a5a26265fa8c9b9.zip |
clk: tegra210: Fix default rates for HDA clocks
[ Upstream commit 9caec6620f25b6d15646bbdb93062c872ba3b56f ]
Currently the default clock rates for the HDA and HDA2CODEC_2X clocks
are both 19.2MHz. However, the default rates for these clocks should
actually be 51MHz and 48MHz, respectively. The current clock settings
results in a distorted output during audio playback. Correct the default
clock rates for these clocks by specifying them in the clock init table
for Tegra210.
Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index f58480fe1767..080bfa24863e 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3376,6 +3376,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 }, + { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 }, + { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 }, /* This MUST be the last entry. */ { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, }; |