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| author | Imran Shaik <quic_imrashai@quicinc.com> | 2023-08-03 16:27:35 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-08-13 20:13:17 -0700 |
| commit | b311f5d3c4749259043a9a458a8db07915210142 (patch) | |
| tree | fb72142c54cae464b921ba17dac278e3512fb033 /drivers/clk | |
| parent | df873243b2398a082d34a006bebe0e0ed7538f5c (diff) | |
| download | linux-stable-b311f5d3c4749259043a9a458a8db07915210142.tar.gz linux-stable-b311f5d3c4749259043a9a458a8db07915210142.tar.bz2 linux-stable-b311f5d3c4749259043a9a458a8db07915210142.zip | |
clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling
Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops
implementation to let the clock framework automatically park the clock
at XO when the clock is switched off and restore the parent when the
clock is switched on.
Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-3-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/gcc-qdu1000.c | 23 |
1 files changed, 6 insertions, 17 deletions
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c index 5051769ad90c..c00d26a3e6df 100644 --- a/drivers/clk/qcom/gcc-qdu1000.c +++ b/drivers/clk/qcom/gcc-qdu1000.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/clk-provider.h> @@ -370,16 +370,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = { { .index = DT_TCXO_IDX }, }; -static const struct parent_map gcc_parent_map_7[] = { - { P_PCIE_0_PIPE_CLK, 0 }, - { P_BI_TCXO, 2 }, -}; - -static const struct clk_parent_data gcc_parent_data_7[] = { - { .index = DT_PCIE_0_PIPE_CLK_IDX }, - { .index = DT_TCXO_IDX }, -}; - static const struct parent_map gcc_parent_map_8[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -439,16 +429,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { }, }; -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x9d064, - .shift = 0, - .width = 2, - .parent_map = gcc_parent_map_7, .clkr = { .hw.init = &(const struct clk_init_data) { .name = "gcc_pcie_0_pipe_clk_src", - .parent_data = gcc_parent_data_7, - .num_parents = ARRAY_SIZE(gcc_parent_data_7), + .parent_data = &(const struct clk_parent_data){ + .index = DT_PCIE_0_PIPE_CLK_IDX, + }, + .num_parents = 1, .ops = &clk_regmap_phy_mux_ops, }, }, |