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authorThierry Reding <treding@nvidia.com>2019-10-16 13:50:26 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-01-04 19:12:38 +0100
commit40179e745ff74de306897b2ebbbb1f877880d464 (patch)
treeeb950ba8fc57f69ea05d12f0cdb1deccd7c1abfd /drivers/dma/xilinx
parenta03f5974f32ced7b85f1a64e66568f9156575924 (diff)
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iommu/tegra-smmu: Fix page tables in > 4 GiB memory
[ Upstream commit 96d3ab802e4930a29a33934373157d6dff1b2c7e ] Page tables that reside in physical memory beyond the 4 GiB boundary are currently not working properly. The reason is that when the physical address for page directory entries is read, it gets truncated at 32 bits and can cause crashes when passing that address to the DMA API. Fix this by first casting the PDE value to a dma_addr_t and then using the page frame number mask for the SMMU instance to mask out the invalid bits, which are typically used for mapping attributes, etc. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/dma/xilinx')
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