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| author | Carlos Palminha <palminha@synopsys.com> | 2016-02-19 15:30:26 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2016-04-26 17:58:02 +0300 |
| commit | 51dacf208988e5a2561d9b4b560cacc8a7f025e7 (patch) | |
| tree | 0c4250e7b15eaf1b711a9bd83fa2fe0c14447d79 /drivers/gpu/drm/arc/arcpgu_regs.h | |
| parent | 027b3f8ba9277410c3191d72d1ed2c6146d8a668 (diff) | |
| download | linux-stable-51dacf208988e5a2561d9b4b560cacc8a7f025e7.tar.gz linux-stable-51dacf208988e5a2561d9b4b560cacc8a7f025e7.tar.bz2 linux-stable-51dacf208988e5a2561d9b4b560cacc8a7f025e7.zip | |
drm: Add support of ARC PGU display controller
ARC PGU could be found on some development boards from Synopsys.
This is a simple byte streamer that reads data from a framebuffer
and sends data to the single encoder.
Signed-off-by: Carlos Palminha <palminha@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-snps-arc@lists.infradead.org
Diffstat (limited to 'drivers/gpu/drm/arc/arcpgu_regs.h')
| -rw-r--r-- | drivers/gpu/drm/arc/arcpgu_regs.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/gpu/drm/arc/arcpgu_regs.h b/drivers/gpu/drm/arc/arcpgu_regs.h new file mode 100644 index 000000000000..95a13a84c373 --- /dev/null +++ b/drivers/gpu/drm/arc/arcpgu_regs.h @@ -0,0 +1,40 @@ +/* + * ARC PGU DRM driver. + * + * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ARC_PGU_REGS_H_ +#define _ARC_PGU_REGS_H_ + +#define ARCPGU_REG_CTRL 0x00 +#define ARCPGU_REG_STAT 0x04 +#define ARCPGU_REG_FMT 0x10 +#define ARCPGU_REG_HSYNC 0x14 +#define ARCPGU_REG_VSYNC 0x18 +#define ARCPGU_REG_ACTIVE 0x1c +#define ARCPGU_REG_BUF0_ADDR 0x40 +#define ARCPGU_REG_STRIDE 0x50 +#define ARCPGU_REG_START_SET 0x84 + +#define ARCPGU_REG_ID 0x3FC + +#define ARCPGU_CTRL_ENABLE_MASK 0x02 +#define ARCPGU_CTRL_VS_POL_MASK 0x1 +#define ARCPGU_CTRL_VS_POL_OFST 0x3 +#define ARCPGU_CTRL_HS_POL_MASK 0x1 +#define ARCPGU_CTRL_HS_POL_OFST 0x4 +#define ARCPGU_MODE_RGB888_MASK 0x04 +#define ARCPGU_STAT_BUSY_MASK 0x02 + +#endif |