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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-02-18 19:00:21 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-02-20 01:33:47 +0100 |
| commit | 3f1e109a8be5670487e00e1c6bc0670526325227 (patch) | |
| tree | 32faf68df34b5fd3f6888f3673e5f7b9ab2639f0 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 115bc2de52af131c2c9bb2bda1adde88c9aa8fef (diff) | |
| download | linux-stable-3f1e109a8be5670487e00e1c6bc0670526325227.tar.gz linux-stable-3f1e109a8be5670487e00e1c6bc0670526325227.tar.bz2 linux-stable-3f1e109a8be5670487e00e1c6bc0670526325227.zip | |
drm/i915: use FPGA_DBG for the "unclaimed register" checks
We plan to treat GEN7_ERR_INT as an interrupt, so use this register
for the checks inside I915_WRITE. This way we can have the best of
both worlds: the error message with a register address and the
V2: Split in 2 patches: one for the macro, one for changing the
register, as requested by Ben.
V3: Rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 527b664d3434..9e5844b2f1f5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -522,6 +522,9 @@ #define GEN7_ERR_INT 0x44040 #define ERR_INT_MMIO_UNCLAIMED (1<<13) +#define FPGA_DBG 0x42300 +#define FPGA_DBG_RM_NOCLAIM (1<<31) + #define DERRMR 0x44050 /* GM45+ chicken bits -- debug workaround bits that may be required |