diff options
| author | Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> | 2018-08-24 16:08:44 -0700 |
|---|---|---|
| committer | Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> | 2018-08-27 12:08:04 -0700 |
| commit | 65df9c7947d70a8d78b2af5a1a835c713110d21e (patch) | |
| tree | 3005a2ea12068485528059ff225a627b24fbf08e /drivers/gpu/drm/i915/intel_psr.c | |
| parent | fd255f6e3704d183f6f5011efd01fcda70372cab (diff) | |
| download | linux-stable-65df9c7947d70a8d78b2af5a1a835c713110d21e.tar.gz linux-stable-65df9c7947d70a8d78b2af5a1a835c713110d21e.tar.bz2 linux-stable-65df9c7947d70a8d78b2af5a1a835c713110d21e.zip | |
drm/i915/psr: Rewrite comments in intel_psr_wait_for_idle()
Added bspec reference, aligned text and documented the function.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180824230844.12428-2-dhinakaran.pandiyan@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_psr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_psr.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 2cb931f3019b..aee64aee18fe 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -766,6 +766,16 @@ void intel_psr_disable(struct intel_dp *intel_dp, cancel_work_sync(&dev_priv->psr.work); } +/** + * intel_psr_wait_for_idle - wait for PSR1 to idle + * @new_crtc_state: new CRTC state + * @out_value: PSR status in case of failure + * + * This function is expected to be called from pipe_update_start() where it is + * not expected to race with PSR enable or disable. + * + * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. + */ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, u32 *out_value) { @@ -775,25 +785,15 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) return 0; - /* - * The sole user right now is intel_pipe_update_start(), - * which won't race with psr_enable/disable, which is - * where psr2_enabled is written to. So, we don't need - * to acquire the psr.lock. More importantly, we want the - * latency inside intel_pipe_update_start() to be as low - * as possible, so no need to acquire psr.lock when it is - * not needed and will induce latencies in the atomic - * update path. - */ - /* FIXME: Update this for PSR2 if we need to wait for idle */ if (READ_ONCE(dev_priv->psr.psr2_enabled)) return 0; /* - * Max time for PSR to idle = Inverse of the refresh rate + - * 6 ms of exit training time + 1.5 ms of aux channel - * handshake. 50 msec is defesive enough to cover everything. + * From bspec: Panel Self Refresh (BDW+) + * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of + * exit training time + 1.5 ms of aux channel handshake. 50 ms is + * defensive enough to cover everything. */ return __intel_wait_for_register(dev_priv, EDP_PSR_STATUS, |