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| author | José Roberto de Souza <jose.souza@intel.com> | 2018-10-03 13:50:25 -0700 |
|---|---|---|
| committer | Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> | 2018-10-05 16:10:12 -0700 |
| commit | bf80928fbf066826251a9f3f7543ada52cc69c92 (patch) | |
| tree | c30ec02195f55a1f35d17927770bb26f08c1c1ee /drivers/gpu/drm/i915/intel_psr.c | |
| parent | 00e5d8b1eb47378924f3de3435450650f426b02a (diff) | |
| download | linux-stable-bf80928fbf066826251a9f3f7543ada52cc69c92.tar.gz linux-stable-bf80928fbf066826251a9f3f7543ada52cc69c92.tar.bz2 linux-stable-bf80928fbf066826251a9f3f7543ada52cc69c92.zip | |
drm/i915/psr: Share PSR and PSR2 exit mask
Now both PSR and PSR2 have the same exit mask, so let's share then
instead of have the same code 2 times.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181003205031.32474-1-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_psr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_psr.c | 34 |
1 files changed, 13 insertions, 21 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 83528647b40b..102da7aae9d8 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -580,28 +580,20 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, else chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL; I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); - - I915_WRITE(EDP_PSR_DEBUG, - EDP_PSR_DEBUG_MASK_MEMUP | - EDP_PSR_DEBUG_MASK_HPD | - EDP_PSR_DEBUG_MASK_LPSP | - EDP_PSR_DEBUG_MASK_MAX_SLEEP | - EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); - } else { - /* - * Per Spec: Avoid continuous PSR exit by masking MEMUP - * and HPD. also mask LPSP to avoid dependency on other - * drivers that might block runtime_pm besides - * preventing other hw tracking issues now we can rely - * on frontbuffer tracking. - */ - I915_WRITE(EDP_PSR_DEBUG, - EDP_PSR_DEBUG_MASK_MEMUP | - EDP_PSR_DEBUG_MASK_HPD | - EDP_PSR_DEBUG_MASK_LPSP | - EDP_PSR_DEBUG_MASK_DISP_REG_WRITE | - EDP_PSR_DEBUG_MASK_MAX_SLEEP); } + + /* + * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also + * mask LPSP to avoid dependency on other drivers that might block + * runtime_pm besides preventing other hw tracking issues now we + * can rely on frontbuffer tracking. + */ + I915_WRITE(EDP_PSR_DEBUG, + EDP_PSR_DEBUG_MASK_MEMUP | + EDP_PSR_DEBUG_MASK_HPD | + EDP_PSR_DEBUG_MASK_LPSP | + EDP_PSR_DEBUG_MASK_DISP_REG_WRITE | + EDP_PSR_DEBUG_MASK_MAX_SLEEP); } static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, |