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authorDaniel Vetter <daniel.vetter@ffwll.ch>2014-09-30 22:36:57 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-09-30 22:36:57 +0200
commit955e36d0b4d3e29c9c8a865d166a42718aed302e (patch)
tree9913b327cc443e5eb3d399eafb9d460d9261d2f2 /drivers/gpu/drm/i915/intel_ringbuffer.c
parentce31d9f4fc05964f6c0dd3a8661dc1a1d843a1e2 (diff)
parentc83155a6044341d67b85b441ba719f86058f6e2b (diff)
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Merge branch 'topic/skl-stage1' into drm-intel-next-queued
SKL stage 1 patches still need polish so will likely miss the 3.18 merge window. We've decided to postpone to 3.19 so let's pull this in to make patch merging and conflict handling easier. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c21aaad55982..cc50bf65d35a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -827,7 +827,7 @@ static int init_render_ring(struct intel_engine_cs *ring)
*
* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
*/
- if (INTEL_INFO(dev)->gen >= 6)
+ if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
/* Required for the hardware to program scanline values for waiting */