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| author | Kenneth Graunke <kenneth@whitecape.org> | 2015-01-13 12:46:53 -0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-01-17 05:01:28 +0100 |
| commit | 973a5b06a096f1a9494ebe94c78d809459f4dc74 (patch) | |
| tree | b0a265eb0ad15d2754e2f1b5435f5a16a0c629f8 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | 2701fc43562b55f5db0139ef6a7b13c2518ed6c0 (diff) | |
| download | linux-stable-973a5b06a096f1a9494ebe94c78d809459f4dc74.tar.gz linux-stable-973a5b06a096f1a9494ebe94c78d809459f4dc74.tar.bz2 linux-stable-973a5b06a096f1a9494ebe94c78d809459f4dc74.zip | |
drm/i915: Ensure the HiZ RAW Stall Optimization is on for Cherryview.
This is an important optimization for avoiding read-after-write (RAW)
stalls in the HiZ buffer. Certain workloads would run very slowly with
HiZ enabled, but run much faster with the "hiz=false" driconf option.
With this patch, they run at full speed even with HiZ.
Increases performance in OglVSInstancing by about 2.7x on Braswell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 0df15a4ad47f..23020d67329b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -846,6 +846,11 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) HDC_FORCE_NON_COHERENT | HDC_DONOT_FETCH_MEM_WHEN_MASKED); + /* According to the CACHE_MODE_0 default value documentation, some + * CHV platforms disable this optimization by default. Turn it on. + */ + WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); + /* Improve HiZ throughput on CHV. */ WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); |