diff options
| author | Michal Wajdeczko <michal.wajdeczko@intel.com> | 2017-04-07 16:01:45 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2017-04-07 18:48:41 +0100 |
| commit | bea4e4a4f831df1c104be60b3caa7205ba1bb4f9 (patch) | |
| tree | 700bbcaee188f1a7835707329f095fbf0fe42dcd /drivers/gpu/drm/i915/intel_uc.c | |
| parent | 1d1a9774e40414148ecebbdb713746bfb6f9a561 (diff) | |
| download | linux-stable-bea4e4a4f831df1c104be60b3caa7205ba1bb4f9.tar.gz linux-stable-bea4e4a4f831df1c104be60b3caa7205ba1bb4f9.tar.bz2 linux-stable-bea4e4a4f831df1c104be60b3caa7205ba1bb4f9.zip | |
drm/i915/guc: Use wait_for_register_fw() while waiting for MMIO response
Waiting for the response status in scratch register can be done
using our generic function. Let's use it.
v2: rebased
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20170407160145.181328-2-michal.wajdeczko@intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_uc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_uc.c | 26 |
1 files changed, 7 insertions, 19 deletions
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index c117424f1f50..4364b1a9064e 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -360,19 +360,6 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv) } /* - * Read GuC command/status register (SOFT_SCRATCH_0) - * Return true if it contains a response rather than a command - */ -static bool guc_recv(struct intel_guc *guc, u32 *status) -{ - struct drm_i915_private *dev_priv = guc_to_i915(guc); - - u32 val = I915_READ(SOFT_SCRATCH(0)); - *status = val; - return INTEL_GUC_RECV_IS_RESPONSE(val); -} - -/* * This function implements the MMIO based host to GuC interface. */ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len) @@ -399,13 +386,14 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len) I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER); /* - * Fast commands should complete in less than 10us, so sample quickly - * up to that length of time, then switch to a slower sleep-wait loop. - * No inte_guc_send command should ever take longer than 10ms. + * No GuC command should ever take longer than 10ms. + * Fast commands should still complete in 10us. */ - ret = wait_for_us(guc_recv(guc, &status), 10); - if (ret) - ret = wait_for(guc_recv(guc, &status), 10); + ret = __intel_wait_for_register_fw(dev_priv, + SOFT_SCRATCH(0), + INTEL_GUC_RECV_MASK, + INTEL_GUC_RECV_MASK, + 10, 10, &status); if (status != INTEL_GUC_STATUS_SUCCESS) { /* * Either the GuC explicitly returned an error (which |