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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2018-01-30 11:49:18 -0200
committerPaulo Zanoni <paulo.r.zanoni@intel.com>2018-01-31 14:30:44 -0200
commit164daaf23c97d949ff6642584c1770b1f9b8974a (patch)
tree8f6c3d9bc9f0c1cb315221a9fbff2386421d82dd /drivers/gpu/drm/i915/intel_uncore.c
parent225701fc20ef9c0219a1119a9495c39c30797a4b (diff)
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drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP register
This enables the Mesa driver to advertise support for ARB_timer_query, and thus an OpenGL version higher than 3.2. Based on the CNL patch by Nanley Chery. v2: Rebase. Cc: Anuj Phogat <anuj.phogat@intel.com> Cc: Nanley Chery <nanley.g.chery@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Requested-by: Anuj Phogat <anuj.phogat@intel.com> Tested-by: Anuj Phogat <anuj.phogat@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130134918.32283-10-paulo.r.zanoni@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_uncore.c')
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 94e1fb3a2936..4075010ac088 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1452,7 +1452,7 @@ static const struct reg_whitelist {
} reg_read_whitelist[] = { {
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
- .gen_mask = INTEL_GEN_MASK(4, 10),
+ .gen_mask = INTEL_GEN_MASK(4, 11),
.size = 8
} };