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| author | Douglas Anderson <dianders@chromium.org> | 2019-07-11 13:34:55 -0700 |
|---|---|---|
| committer | Sam Ravnborg <sam@ravnborg.org> | 2019-07-12 07:55:47 +0200 |
| commit | 374bf825e7a07b6ae61a8a839c0ea184a7665267 (patch) | |
| tree | b475a026f326f070e85a72eaa0ceb929994a2436 /drivers/gpu/drm/panel | |
| parent | d719cbe9a5b39437c442836a6fd5e7b178bcee4d (diff) | |
| download | linux-stable-374bf825e7a07b6ae61a8a839c0ea184a7665267.tar.gz linux-stable-374bf825e7a07b6ae61a8a839c0ea184a7665267.tar.bz2 linux-stable-374bf825e7a07b6ae61a8a839c0ea184a7665267.zip | |
drm/panel: simple: Use display_timing for AUO b101ean01
Convert the AUO b101ean01 from using a fixed mode to specifying a
display timing with min/typ/max values.
The AUO b101ean01's datasheet says:
* Vertical blanking min is 12
* Horizontal blanking min is 60
* Pixel clock is between 65.3 MHz and 75 MHz
The goal here is to be able to specify the proper timing in device
tree to use on rk3288-veyron-minnie to match what the downstream
kernel is using so that it can used the fixed PLL.
Changes in v4:
- display_timing for AUO b101ean01 new for v4.
Changes in v6:
- Rebased to drm-misc next
- Added tags
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711203455.125667-4-dianders@chromium.org
Diffstat (limited to 'drivers/gpu/drm/panel')
| -rw-r--r-- | drivers/gpu/drm/panel/panel-simple.c | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 602809f6da6a..226f068fb679 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -595,22 +595,21 @@ static const struct panel_desc auo_b101aw03 = { }, }; -static const struct drm_display_mode auo_b101ean01_mode = { - .clock = 72500, - .hdisplay = 1280, - .hsync_start = 1280 + 119, - .hsync_end = 1280 + 119 + 32, - .htotal = 1280 + 119 + 32 + 21, - .vdisplay = 800, - .vsync_start = 800 + 4, - .vsync_end = 800 + 4 + 20, - .vtotal = 800 + 4 + 20 + 8, - .vrefresh = 60, +static const struct display_timing auo_b101ean01_timing = { + .pixelclock = { 65300000, 72500000, 75000000 }, + .hactive = { 1280, 1280, 1280 }, + .hfront_porch = { 18, 119, 119 }, + .hback_porch = { 21, 21, 21 }, + .hsync_len = { 32, 32, 32 }, + .vactive = { 800, 800, 800 }, + .vfront_porch = { 4, 4, 4 }, + .vback_porch = { 8, 8, 8 }, + .vsync_len = { 18, 20, 20 }, }; static const struct panel_desc auo_b101ean01 = { - .modes = &auo_b101ean01_mode, - .num_modes = 1, + .timings = &auo_b101ean01_timing, + .num_timings = 1, .bpc = 6, .size = { .width = 217, |