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| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2018-07-11 13:40:17 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-07-15 13:52:56 +0200 |
| commit | ef32df53b73bd29d5bfa4af4fda287baa6dc6544 (patch) | |
| tree | 0b98790d6e51428b04357fc76c174cd1d8b6a981 /drivers/hwtracing | |
| parent | 0f728a7f9f8fed5dfd86a628d871d572cb91942c (diff) | |
| download | linux-stable-ef32df53b73bd29d5bfa4af4fda287baa6dc6544.tar.gz linux-stable-ef32df53b73bd29d5bfa4af4fda287baa6dc6544.tar.bz2 linux-stable-ef32df53b73bd29d5bfa4af4fda287baa6dc6544.zip | |
coresight: tmc-etr: Disallow perf mode
We don't support ETR in perf mode yet. So, don't
even try to enable the hardware, even by mistake.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/hwtracing')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-tmc-etr.c | 28 |
1 files changed, 2 insertions, 26 deletions
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 1de05c9a01c8..18c9a184d31a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -211,32 +211,8 @@ out: static int tmc_enable_etr_sink_perf(struct coresight_device *csdev) { - int ret = 0; - unsigned long flags; - struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - spin_lock_irqsave(&drvdata->spinlock, flags); - if (drvdata->reading) { - ret = -EINVAL; - goto out; - } - - /* - * In Perf mode there can be only one writer per sink. There - * is also no need to continue if the ETR is already operated - * from sysFS. - */ - if (drvdata->mode != CS_MODE_DISABLED) { - ret = -EINVAL; - goto out; - } - - drvdata->mode = CS_MODE_PERF; - tmc_etr_enable_hw(drvdata); -out: - spin_unlock_irqrestore(&drvdata->spinlock, flags); - - return ret; + /* We don't support perf mode yet ! */ + return -EINVAL; } static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) |