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authorWill Deacon <will@kernel.org>2020-01-10 12:22:16 +0000
committerWill Deacon <will@kernel.org>2020-01-10 15:52:24 +0000
commit6f932ad369a3c3f853ffc5d93de9a73420e862b1 (patch)
tree5b148da842f0e636f939e4e4c803654ac8351d22 /drivers/iommu/io-pgtable-arm.c
parent7618e479098226799207e021e8b0c2c28a23c96b (diff)
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iommu/io-pgtable-arm: Ensure ARM_64_LPAE_S2_TCR_RES1 is unsigned
ARM_64_LPAE_S2_TCR_RES1 is intended to map to bit 31 of the VTCR register, which is required to be set to 1 by the architecture. Unfortunately, we accidentally treat this as a signed quantity which means we also set the upper 32 bits of the VTCR to one, and they are required to be zero. Treat ARM_64_LPAE_S2_TCR_RES1 as unsigned to avoid the unwanted sign-extension up to 64 bits. Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/iommu/io-pgtable-arm.c')
-rw-r--r--drivers/iommu/io-pgtable-arm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 1da0d82444f9..1c0ec16effbb 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -101,7 +101,7 @@
/* Register bits */
#define ARM_32_LPAE_TCR_EAE (1 << 31)
-#define ARM_64_LPAE_S2_TCR_RES1 (1 << 31)
+#define ARM_64_LPAE_S2_TCR_RES1 (1U << 31)
#define ARM_LPAE_TCR_EPD1 (1 << 23)