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| author | Robin Murphy <robin.murphy@arm.com> | 2019-10-25 19:08:37 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-01-10 15:39:23 +0000 |
| commit | d1e5f26f14272b5039cc198569ec4fabed14e6db (patch) | |
| tree | 356c25d1b1762b46f6572573aff0e67a557dd4b6 /drivers/iommu/ipmmu-vmsa.c | |
| parent | cd037ff2f98227148002084d588f03b348469fe4 (diff) | |
| download | linux-stable-d1e5f26f14272b5039cc198569ec4fabed14e6db.tar.gz linux-stable-d1e5f26f14272b5039cc198569ec4fabed14e6db.tar.bz2 linux-stable-d1e5f26f14272b5039cc198569ec4fabed14e6db.zip | |
iommu/io-pgtable-arm: Rationalise TTBRn handling
TTBR1 values have so far been redundant since no users implement any
support for split address spaces. Crucially, though, one of the main
reasons for wanting to do so is to be able to manage each half entirely
independently, e.g. context-switching one set of mappings without
disturbing the other. Thus it seems unlikely that tying two tables
together in a single io_pgtable_cfg would ever be particularly desirable
or useful.
Streamline the configs to just a single conceptual TTBR value
representing the allocated table. This paves the way for future users to
support split address spaces by simply allocating a table and dealing
with the detailed TTBRn logistics themselves.
Tested-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
[will: Drop change to ttbr value]
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/iommu/ipmmu-vmsa.c')
| -rw-r--r-- | drivers/iommu/ipmmu-vmsa.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index d02edd2751f3..ecb3f9464dd5 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -374,7 +374,7 @@ static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain) u32 tmp; /* TTBR0 */ - ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0]; + ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); |