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author | Hanjun Guo <hanjun.guo@linaro.org> | 2015-03-24 14:02:48 +0000 |
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committer | Will Deacon <will.deacon@arm.com> | 2015-03-26 15:13:07 +0000 |
commit | fbe61ec71ac975279cd47b6c299d5e33f63aac4e (patch) | |
tree | 1a0b6128e7901e1b0fb8639c1347cff4a2cac4cf /drivers/irqchip/irqchip.c | |
parent | 020295b4cb5b7d510ea1f4531a502c3f8a2380c5 (diff) | |
download | linux-stable-fbe61ec71ac975279cd47b6c299d5e33f63aac4e.tar.gz linux-stable-fbe61ec71ac975279cd47b6c299d5e33f63aac4e.tar.bz2 linux-stable-fbe61ec71ac975279cd47b6c299d5e33f63aac4e.zip |
ARM64 / ACPI: Introduce ACPI_IRQ_MODEL_GIC and register device's gsi
Introduce ACPI_IRQ_MODEL_GIC which is needed for ARM64 as GIC is
used, and then register device's gsi with the core IRQ subsystem.
acpi_register_gsi() is similar to DT based irq_of_parse_and_map(),
since gsi is unique in the system, so use hwirq number directly
for the mapping.
We are going to implement stacked domains when GICv2m, GICv3, ITS
support are added.
CC: Marc Zyngier <marc.zyngier@arm.com>
Originally-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Tested-by: Yijing Wang <wangyijing@huawei.com>
Tested-by: Mark Langsdorf <mlangsdo@redhat.com>
Tested-by: Jon Masters <jcm@redhat.com>
Tested-by: Timur Tabi <timur@codeaurora.org>
Tested-by: Robert Richter <rrichter@cavium.com>
Acked-by: Robert Richter <rrichter@cavium.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Grant Likely <grant.likely@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/irqchip/irqchip.c')
0 files changed, 0 insertions, 0 deletions