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| author | Jon Hunter <jonathanh@nvidia.com> | 2016-02-09 15:24:57 +0000 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2016-02-11 10:20:02 +0000 |
| commit | 389a00d3ad02a06b5d6d692cce76fed6a3dae8b4 (patch) | |
| tree | 542435c6bdb04f0ffe0434773214be768e365394 /drivers/irqchip | |
| parent | 7bf29d3af6807d2a97a8b7d4627104a8da9bcdcb (diff) | |
| download | linux-stable-389a00d3ad02a06b5d6d692cce76fed6a3dae8b4.tar.gz linux-stable-389a00d3ad02a06b5d6d692cce76fed6a3dae8b4.tar.bz2 linux-stable-389a00d3ad02a06b5d6d692cce76fed6a3dae8b4.zip | |
irqchip/gic: Only set the EOImodeNS bit for the root controller
EOImode1 is only used for the root controller and hence only the root
controller uses the eoimode1 functions for handling interrupts. However,
if the root controller supports EOImode1, then the EOImodeNS bit will be
set for all GICs, enabling EOImode1. This is not what we want and this
causes interrupts on non-root GICs to only be dropped in priority but
never deactivated. Therefore, only set the EOImodeNS bit for the root
controller.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip')
| -rw-r--r-- | drivers/irqchip/irq-gic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index db7b161b0295..8f9ebf714e2b 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -437,7 +437,7 @@ static void gic_cpu_if_up(struct gic_chip_data *gic) u32 bypass = 0; u32 mode = 0; - if (static_key_true(&supports_deactivate)) + if (gic == &gic_data[0] && static_key_true(&supports_deactivate)) mode = GIC_CPU_CTRL_EOImodeNS; /* |