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authorSakari Ailus <sakari.ailus@linux.intel.com>2020-06-23 13:40:32 +0200
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>2020-12-07 15:56:17 +0100
commit4e1e8d240dff96bd8dd2c00c5fcd7f04088ace3c (patch)
treeb5738c25e951292d6dd82a158af6d0ef54f73a88 /drivers/media/i2c/ccs-pll.c
parentae502e08f45e47460406ab5c5fd2167a1011499a (diff)
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media: ccs-pll: Add support for extended input PLL clock divider
CCS allows odd PLL dividers other than 1, granted that the corresponding capability bit is set. Support this both in the PLL calculator and the CCS driver. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ccs-pll.c')
-rw-r--r--drivers/media/i2c/ccs-pll.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index cb19a36e54df..62939ca5b8e2 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -478,7 +478,9 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div;
op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div;
- op_pll_fr->pre_pll_clk_div += 2 - (op_pll_fr->pre_pll_clk_div & 1)) {
+ op_pll_fr->pre_pll_clk_div +=
+ (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
+ 2 - (op_pll_fr->pre_pll_clk_div & 1)) {
rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll,
op_pll_fr, op_pll_bk, mul, div);
if (rval)