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| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-06-05 22:46:54 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 15:35:40 +0100 |
| commit | 415ddd9939783cb79790aba1833ea39fd335caed (patch) | |
| tree | 93ab16db937a70a20df6d44171656f8ef90ac5f5 /drivers/media/i2c/ccs-pll.h | |
| parent | c3833a228cef7121cb7fc64d5ef71eedcc6f2f01 (diff) | |
| download | linux-stable-415ddd9939783cb79790aba1833ea39fd335caed.tar.gz linux-stable-415ddd9939783cb79790aba1833ea39fd335caed.tar.bz2 linux-stable-415ddd9939783cb79790aba1833ea39fd335caed.zip | |
media: ccs-pll: Split limits and PLL configuration into front and back parts
The CCS spec supports a lot of variation in the PLL. Split the PLL in
front and back parts to better prepare for supporting it.
Also use CCS compliant naming for IP and OP PLL frequencies (i.e. include
"clk" in the name).
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ccs-pll.h')
| -rw-r--r-- | drivers/media/i2c/ccs-pll.h | 44 |
1 files changed, 26 insertions, 18 deletions
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 07f7f9e8a1cc..03b1d8d11423 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -20,7 +20,14 @@ #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) #define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1) -struct ccs_pll_branch { +struct ccs_pll_branch_fr { + uint16_t pre_pll_clk_div; + uint16_t pll_multiplier; + uint32_t pll_ip_clk_freq_hz; + uint32_t pll_op_clk_freq_hz; +}; + +struct ccs_pll_branch_bk { uint16_t sys_clk_div; uint16_t pix_clk_div; uint32_t sys_clk_freq_hz; @@ -48,18 +55,26 @@ struct ccs_pll { uint32_t ext_clk_freq_hz; /* output values */ - uint16_t pre_pll_clk_div; - uint16_t pll_multiplier; - uint32_t pll_ip_clk_freq_hz; - uint32_t pll_op_clk_freq_hz; - struct ccs_pll_branch vt; - struct ccs_pll_branch op; + struct ccs_pll_branch_fr vt_fr; + struct ccs_pll_branch_bk vt_bk; + struct ccs_pll_branch_bk op_bk; uint32_t pixel_rate_csi; uint32_t pixel_rate_pixel_array; }; -struct ccs_pll_branch_limits { +struct ccs_pll_branch_limits_fr { + uint16_t min_pre_pll_clk_div; + uint16_t max_pre_pll_clk_div; + uint32_t min_pll_ip_clk_freq_hz; + uint32_t max_pll_ip_clk_freq_hz; + uint16_t min_pll_multiplier; + uint16_t max_pll_multiplier; + uint32_t min_pll_op_clk_freq_hz; + uint32_t max_pll_op_clk_freq_hz; +}; + +struct ccs_pll_branch_limits_bk { uint16_t min_sys_clk_div; uint16_t max_sys_clk_div; uint32_t min_sys_clk_freq_hz; @@ -74,17 +89,10 @@ struct ccs_pll_limits { /* Strict PLL limits */ uint32_t min_ext_clk_freq_hz; uint32_t max_ext_clk_freq_hz; - uint16_t min_pre_pll_clk_div; - uint16_t max_pre_pll_clk_div; - uint32_t min_pll_ip_freq_hz; - uint32_t max_pll_ip_freq_hz; - uint16_t min_pll_multiplier; - uint16_t max_pll_multiplier; - uint32_t min_pll_op_freq_hz; - uint32_t max_pll_op_freq_hz; - struct ccs_pll_branch_limits vt; - struct ccs_pll_branch_limits op; + struct ccs_pll_branch_limits_fr vt_fr; + struct ccs_pll_branch_limits_bk vt_bk; + struct ccs_pll_branch_limits_bk op_bk; /* Other relevant limits */ uint32_t min_line_length_pck_bin; |