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| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-08-25 00:06:26 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 17:03:56 +0100 |
| commit | 900c33e86e4b53e96e6ea10e9737870e03911a66 (patch) | |
| tree | 8dff709510edc0705b6368f05058a6fccf46cf94 /drivers/media/i2c/ccs-pll.h | |
| parent | b41f270841f85b9b4f8530b9f2020ff3ba1cfec5 (diff) | |
| download | linux-stable-900c33e86e4b53e96e6ea10e9737870e03911a66.tar.gz linux-stable-900c33e86e4b53e96e6ea10e9737870e03911a66.tar.bz2 linux-stable-900c33e86e4b53e96e6ea10e9737870e03911a66.zip | |
media: ccs-pll: Add support for DDR OP system and pixel clocks
Add support for dual data rate operational system and pixel clocks. This
is implemented using two PLL flags.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ccs-pll.h')
| -rw-r--r-- | drivers/media/i2c/ccs-pll.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 517ee504f44a..b97d7ff50ea5 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -30,6 +30,8 @@ #define CCS_PLL_FLAG_FIFO_DERATING BIT(6) #define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7) #define CCS_PLL_FLAG_DUAL_PLL BIT(8) +#define CCS_PLL_FLAG_OP_SYS_DDR BIT(9) +#define CCS_PLL_FLAG_OP_PIX_DDR BIT(10) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) |