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| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-08-07 11:00:59 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 15:57:07 +0100 |
| commit | c4c0b222720d413cc866275a0200019eb3c58f33 (patch) | |
| tree | 9b3469ff28633d2ef2fcdd1df09ba8794e18ba51 /drivers/media/i2c/ccs-pll.h | |
| parent | 4e1e8d240dff96bd8dd2c00c5fcd7f04088ace3c (diff) | |
| download | linux-stable-c4c0b222720d413cc866275a0200019eb3c58f33.tar.gz linux-stable-c4c0b222720d413cc866275a0200019eb3c58f33.tar.bz2 linux-stable-c4c0b222720d413cc866275a0200019eb3c58f33.zip | |
media: ccs-pll: Support two cycles per pixel on OP domain
The l parameter defines the number of clock cycles to process a single
pixel per OP lane. It is calculated based on a new register
op_bits_per_lane.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ccs-pll.h')
| -rw-r--r-- | drivers/media/i2c/ccs-pll.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 807ae7250aa2..207822cf2324 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -76,6 +76,7 @@ struct ccs_pll_branch_bk { * @scale_m: Downscaling factor, M component, [16, max] (input) * @scale_n: Downscaling factor, N component, typically 16 (input) * @bits_per_pixel: Bits per pixel on the output data bus (input) + * @op_bits_per_lane: Number of bits per OP lane (input) * @flags: CCS_PLL_FLAG_* (input) * @link_freq: Chosen link frequency (input) * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock @@ -100,6 +101,7 @@ struct ccs_pll { uint8_t scale_m; uint8_t scale_n; uint8_t bits_per_pixel; + uint8_t op_bits_per_lane; uint16_t flags; uint32_t link_freq; uint32_t ext_clk_freq_hz; |