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| author | Jia-Ju Bai <baijiaju1990@gmail.com> | 2018-07-26 22:58:43 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-07-27 08:11:13 -0400 |
| commit | 2b5c5798750180a34cb1f39cf648d8a8bceec287 (patch) | |
| tree | e61aebc09199fb5676d25cb3cb35e21e7edcc4df /drivers/media/i2c | |
| parent | 17f330ce9e434333a98b0fbc7b6d5ddbe0cc6770 (diff) | |
| download | linux-stable-2b5c5798750180a34cb1f39cf648d8a8bceec287.tar.gz linux-stable-2b5c5798750180a34cb1f39cf648d8a8bceec287.tar.bz2 linux-stable-2b5c5798750180a34cb1f39cf648d8a8bceec287.zip | |
media: i2c: adv7842: Replace mdelay() with msleep() and usleep_range() in adv7842_ddr_ram_test()
adv7842_ddr_ram_test() is never called in atomic context.
It only calls from:
adv7842_ddr_ram_test() <- adv7842_command_ram_test() <- adv7842_ioctl()
adv7842_ddr_ram_test() calls mdelay() to busily wait,
which is not necessary.
mdelay() can be replaced with msleep() and usleep_range().
This is found by a static analysis tool named DCNS written by myself.
Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'drivers/media/i2c')
| -rw-r--r-- | drivers/media/i2c/adv7842.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/media/i2c/adv7842.c b/drivers/media/i2c/adv7842.c index 99d781343fb1..4f8fbdd00e35 100644 --- a/drivers/media/i2c/adv7842.c +++ b/drivers/media/i2c/adv7842.c @@ -3102,7 +3102,7 @@ static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */ io_write(sd, 0xFF, 0x04); /* Reset memory controller */ - mdelay(5); + usleep_range(5000, 6000); sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */ sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */ @@ -3116,12 +3116,12 @@ static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */ sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */ - mdelay(5); + usleep_range(5000, 6000); sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */ sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */ - mdelay(20); + msleep(20); for (i = 0; i < 10; i++) { u8 result = sdp_io_read(sd, 0xdb); @@ -3132,7 +3132,7 @@ static int adv7842_ddr_ram_test(struct v4l2_subdev *sd) else pass++; } - mdelay(20); + msleep(20); } v4l2_dbg(1, debug, sd, |