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author | Joerg Roedel <jroedel@suse.de> | 2015-08-17 14:16:59 +0200 |
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committer | Joerg Roedel <jroedel@suse.de> | 2015-08-17 14:16:59 +0200 |
commit | 54e466fde4816455cc5b1893b73c2f3c7ca52e49 (patch) | |
tree | 402e1f22e0053ed4ee8155a5408bd0b1eac11113 /drivers/memory/tegra/tegra124.c | |
parent | 2c6625cd545bdd66acff14f3394865d43920a5c7 (diff) | |
parent | 11cec15bf3fb498206ef63b1fa26c27689e02d0e (diff) | |
download | linux-stable-54e466fde4816455cc5b1893b73c2f3c7ca52e49.tar.gz linux-stable-54e466fde4816455cc5b1893b73c2f3c7ca52e49.tar.bz2 linux-stable-54e466fde4816455cc5b1893b73c2f3c7ca52e49.zip |
Merge tag 'tegra-for-4.3-iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/tegra
iommu/tegra-smmu: Changes for v4.3-rc1
A bunch of improvements by Russell King, along with a fix to restore
display support when using the SMMU. This was due to the SMMU driver
writing the wrong value of active TLB lines, effectively disabling the
TLB and causing massive underflows on the display controller because
of the latency introduced by the SMMU.
Diffstat (limited to 'drivers/memory/tegra/tegra124.c')
-rw-r--r-- | drivers/memory/tegra/tegra124.c | 31 |
1 files changed, 1 insertions, 30 deletions
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index 966e1557e6f4..7d734befe0ed 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -9,8 +9,6 @@ #include <linux/of.h> #include <linux/mm.h> -#include <asm/cacheflush.h> - #include <dt-bindings/memory/tegra124-mc.h> #include "mc.h" @@ -1002,20 +1000,6 @@ static const struct tegra_smmu_swgroup tegra124_swgroups[] = { }; #ifdef CONFIG_ARCH_TEGRA_124_SOC -static void tegra124_flush_dcache(struct page *page, unsigned long offset, - size_t size) -{ - phys_addr_t phys = page_to_phys(page) + offset; - void *virt = page_address(page) + offset; - - __cpuc_flush_dcache_area(virt, size); - outer_flush_range(phys, phys + size); -} - -static const struct tegra_smmu_ops tegra124_smmu_ops = { - .flush_dcache = tegra124_flush_dcache, -}; - static const struct tegra_smmu_soc tegra124_smmu_soc = { .clients = tegra124_mc_clients, .num_clients = ARRAY_SIZE(tegra124_mc_clients), @@ -1024,7 +1008,6 @@ static const struct tegra_smmu_soc tegra124_smmu_soc = { .supports_round_robin_arbitration = true, .supports_request_limit = true, .num_asids = 128, - .ops = &tegra124_smmu_ops, }; const struct tegra_mc_soc tegra124_mc_soc = { @@ -1039,18 +1022,6 @@ const struct tegra_mc_soc tegra124_mc_soc = { #endif /* CONFIG_ARCH_TEGRA_124_SOC */ #ifdef CONFIG_ARCH_TEGRA_132_SOC -static void tegra132_flush_dcache(struct page *page, unsigned long offset, - size_t size) -{ - void *virt = page_address(page) + offset; - - __flush_dcache_area(virt, size); -} - -static const struct tegra_smmu_ops tegra132_smmu_ops = { - .flush_dcache = tegra132_flush_dcache, -}; - static const struct tegra_smmu_soc tegra132_smmu_soc = { .clients = tegra124_mc_clients, .num_clients = ARRAY_SIZE(tegra124_mc_clients), @@ -1058,8 +1029,8 @@ static const struct tegra_smmu_soc tegra132_smmu_soc = { .num_swgroups = ARRAY_SIZE(tegra124_swgroups), .supports_round_robin_arbitration = true, .supports_request_limit = true, + .num_tlb_lines = 32, .num_asids = 128, - .ops = &tegra132_smmu_ops, }; const struct tegra_mc_soc tegra132_mc_soc = { |