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author | Raul E Rangel <rrangel@chromium.org> | 2019-06-17 14:10:13 -0600 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-07-31 07:27:01 +0200 |
commit | 5d3ad905af431fcfd1e51ce97c02c062c076e1a7 (patch) | |
tree | 8082f08b117d7c0d11feebcbc44233b2a63360b5 /drivers/mmc | |
parent | bf7cf9fb02dbe59a3c471bdbe2088355c5946f08 (diff) | |
download | linux-stable-5d3ad905af431fcfd1e51ce97c02c062c076e1a7.tar.gz linux-stable-5d3ad905af431fcfd1e51ce97c02c062c076e1a7.tar.bz2 linux-stable-5d3ad905af431fcfd1e51ce97c02c062c076e1a7.zip |
mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width
[ Upstream commit de23f0b757766d9fae59df97da6e8bdc5b231351 ]
The O2 controller supports 8-bit EMMC access.
JESD84-B51 section A.6.3.a defines the bus testing procedure that
`mmc_select_bus_width()` implements. This is used to determine the actual
bus width of the eMMC.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r-- | drivers/mmc/host/sdhci-pci-o2micro.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c index fa8d9da2ab7f..e248d7945c06 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c @@ -290,11 +290,21 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) { struct sdhci_pci_chip *chip; struct sdhci_host *host; - u32 reg; + u32 reg, caps; int ret; chip = slot->chip; host = slot->host; + + caps = sdhci_readl(host, SDHCI_CAPABILITIES); + + /* + * mmc_select_bus_width() will test the bus to determine the actual bus + * width. + */ + if (caps & SDHCI_CAN_DO_8BIT) + host->mmc->caps |= MMC_CAP_8_BIT_DATA; + switch (chip->pdev->device) { case PCI_DEVICE_ID_O2_SDS0: case PCI_DEVICE_ID_O2_SEABIRD0: |