diff options
| author | Ido Schimmel <idosch@mellanox.com> | 2018-10-11 07:47:57 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-10-11 10:08:22 -0700 |
| commit | beda7f72c36ab4f156e14d785a4bc50ddc2df657 (patch) | |
| tree | b30c5a284a6b26b218868c52dc1e2bed5e0ccbbf /drivers/net/ethernet/mellanox/mlxsw/reg.h | |
| parent | a682a3024fe1d21653876fe2f0b231d011f6a72d (diff) | |
| download | linux-stable-beda7f72c36ab4f156e14d785a4bc50ddc2df657.tar.gz linux-stable-beda7f72c36ab4f156e14d785a4bc50ddc2df657.tar.bz2 linux-stable-beda7f72c36ab4f156e14d785a4bc50ddc2df657.zip | |
mlxsw: spectrum: Seed LAG hash function
Currently, the seed of the LAG hash function is always set to 0, which
means it is identical across all switches. Instead, use a random number.
This is especially important now that VxLAN is supported, as the LAG
hash function is used to calculate the UDP source port of the
encapsulated packet.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Reviewed-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/reg.h')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/reg.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index a0441f3d4284..4988d24a628c 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -1321,12 +1321,19 @@ MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); */ MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); -static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) +/* reg_slcr_seed + * LAG seed value. The seed is the same for all ports. + * Access: RW + */ +MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); + +static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) { MLXSW_REG_ZERO(slcr, payload); mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); + mlxsw_reg_slcr_seed_set(payload, seed); } /* SLCOR - Switch LAG Collector Register |