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| author | Jeff Garzik <jeff@garzik.org> | 2006-09-13 13:24:59 -0400 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2006-09-13 13:24:59 -0400 |
| commit | 6aa20a2235535605db6d6d2bd850298b2fe7f31e (patch) | |
| tree | df0b855043407b831d57f2f2c271f8aab48444f4 /drivers/net/saa9730.h | |
| parent | 7a291083225af6e22ffaa46b3d91cfc1a1ccaab4 (diff) | |
| download | linux-stable-6aa20a2235535605db6d6d2bd850298b2fe7f31e.tar.gz linux-stable-6aa20a2235535605db6d6d2bd850298b2fe7f31e.tar.bz2 linux-stable-6aa20a2235535605db6d6d2bd850298b2fe7f31e.zip | |
drivers/net: Trim trailing whitespace
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/saa9730.h')
| -rw-r--r-- | drivers/net/saa9730.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/net/saa9730.h b/drivers/net/saa9730.h index a7e9d29a86a7..f656f2f40bb8 100644 --- a/drivers/net/saa9730.h +++ b/drivers/net/saa9730.h @@ -34,9 +34,9 @@ /* TX and RX packet size: fixed to 2048 bytes, according to HW requirements. */ #define LAN_SAA9730_PACKET_SIZE 2048 -/* - * Number of TX buffers = number of RX buffers = 2, which is fixed according - * to HW requirements. +/* + * Number of TX buffers = number of RX buffers = 2, which is fixed according + * to HW requirements. */ #define LAN_SAA9730_BUFFERS 2 @@ -47,10 +47,10 @@ #define LAN_SAA9730_TXM_Q_SIZE 15 /* - * We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD - * packets received. + * We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD + * packets received. * If however we receive less than LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD - * packets, the hardware can timeout after a certain time and still tell + * packets, the hardware can timeout after a certain time and still tell * us packets have arrived. * The timeout value in unit of 32 PCI clocks (33Mhz). * The value 200 approximates 0.0002 seconds. @@ -79,8 +79,8 @@ #define MACCM_10MB 1 #define MACCM_MII 2 -/* - * PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board) +/* + * PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board) */ #define PHY_CONTROL 0x0 #define PHY_STATUS 0x1 |