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authorDavid Gounaris <david.gounaris@infinera.com>2018-09-03 14:47:29 +0200
committerDavid S. Miller <davem@davemloft.net>2018-09-03 22:14:41 -0700
commit040b7c94e4ec585149f63f429253a493064749c3 (patch)
tree12d899dca1a07a795f0f1cf540adfcf49bd15bc5 /drivers/net/wan
parent045f77baf6b429a446ace64ba3174783a933398a (diff)
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net/wan/fsl_ucc_hdlc: GUMR for non tsa mode
The following bits in the GUMR is changed for non tsa mode: CDS, CTSP and CTSS are set to zero. When set, there is no tx interrupts from the controller. Signed-off-by: David Gounaris <david.gounaris@infinera.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/wan')
-rw-r--r--drivers/net/wan/fsl_ucc_hdlc.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
index bb52c4dcf22c..4545c782ef4e 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.c
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
@@ -97,6 +97,12 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
if (priv->tsa) {
uf_info->tsa = 1;
uf_info->ctsp = 1;
+ uf_info->cds = 1;
+ uf_info->ctss = 1;
+ } else {
+ uf_info->cds = 0;
+ uf_info->ctsp = 0;
+ uf_info->ctss = 0;
}
/* This sets HPM register in CMXUCR register which configures a