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| author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2015-03-14 11:27:55 +0530 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2015-03-20 08:28:08 +0200 |
| commit | f2ef792a80859ecdabeaf5bf960ad97a9dd81fc6 (patch) | |
| tree | fd1950e889b03ef0fe59e1cf58443ceabb951a36 /drivers/net/wireless/ath/ath9k/ar9003_aic.c | |
| parent | 958b6827b781ed14d12bef6323f6692ec761fbb5 (diff) | |
| download | linux-stable-f2ef792a80859ecdabeaf5bf960ad97a9dd81fc6.tar.gz linux-stable-f2ef792a80859ecdabeaf5bf960ad97a9dd81fc6.tar.bz2 linux-stable-f2ef792a80859ecdabeaf5bf960ad97a9dd81fc6.zip | |
ath9k: Handle MCI_STATE_AIC_START
This patch adds a function to handle the
MCI message MCI_STATE_AIC_START.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_aic.c')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_aic.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_aic.c b/drivers/net/wireless/ath/ath9k/ar9003_aic.c index 4e8cf084d2fa..5b4f818264f5 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_aic.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_aic.c @@ -18,6 +18,7 @@ #include "hw-ops.h" #include "ar9003_mci.h" #include "ar9003_aic.h" +#include "ar9003_phy.h" #include "reg_aic.h" static const u8 com_att_db_table[ATH_AIC_MAX_COM_ATT_DB_TABLE] = { @@ -512,6 +513,38 @@ exit: } +u8 ar9003_aic_start_normal(struct ath_hw *ah) +{ + struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic; + int16_t i; + + if (aic->aic_cal_state != AIC_CAL_STATE_DONE) + return 1; + + ar9003_aic_gain_table(ah); + + REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, ATH_AIC_SRAM_AUTO_INCREMENT); + + for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) { + REG_WRITE(ah, AR_PHY_AIC_SRAM_DATA_B1, aic->aic_sram[i]); + } + + /* FIXME: Replace these with proper register names */ + REG_WRITE(ah, 0xa6b0, 0x80); + REG_WRITE(ah, 0xa6b4, 0x5b2df0); + REG_WRITE(ah, 0xa6b8, 0x10762cc8); + REG_WRITE(ah, 0xa6bc, 0x1219a4b); + REG_WRITE(ah, 0xa6c0, 0x1e01); + REG_WRITE(ah, 0xb6b4, 0xf0); + REG_WRITE(ah, 0xb6c0, 0x1e01); + REG_WRITE(ah, 0xb6b0, 0x81); + REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX4, 0x40000000); + + aic->aic_enabled = true; + + return 0; +} + u8 ar9003_aic_cal_reset(struct ath_hw *ah) { struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic; |