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authorBjorn Helgaas <bhelgaas@google.com>2018-04-17 10:58:09 -0500
committerBjorn Helgaas <bhelgaas@google.com>2018-04-23 08:18:44 -0500
commitaf8bb9f89838249872240f258e67774ccbcc5970 (patch)
treef6f8ae73b8afe586066604ec5228ca99b4bde1af /drivers/pci/probe.c
parent9ab105deb60fa76d66cae5548819b4e8703d2056 (diff)
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PCI/ACPI: Request LTR control from platform before using it
Per the PCI Firmware spec r3.2, sec 4.5, an ACPI-based OS should use _OSC to request control of Latency Tolerance Reporting (LTR) before using it. Request control of LTR, and if the platform does not grant control, don't use it. N.B. If the hardware supports LTR and the ASPM L1.2 substate but the BIOS doesn't support LTR in _OSC, we previously would enable ASPM L1.2. This patch will prevent us from enabling ASPM L1.2 in that case. It does not prevent us from enabling PCI-PM L1.2, since that doesn't depend on LTR. See PCIe r40, sec 5.5.1, for the L1 PM substate entry conditions. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/pci/probe.c')
-rw-r--r--drivers/pci/probe.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ac91b6fd0bcd..cc1688d75664 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -554,6 +554,7 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
bridge->native_aer = 1;
bridge->native_hotplug = 1;
bridge->native_pme = 1;
+ bridge->native_ltr = 1;
return bridge;
}
@@ -1954,9 +1955,13 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev)
static void pci_configure_ltr(struct pci_dev *dev)
{
#ifdef CONFIG_PCIEASPM
+ struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
u32 cap;
struct pci_dev *bridge;
+ if (!host->native_ltr)
+ return;
+
if (!pci_is_pcie(dev))
return;