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| author | Bjorn Andersson <bjorn.andersson@linaro.org> | 2021-11-03 16:44:10 -0700 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-11-23 10:40:17 +0530 |
| commit | f199223cb490be108e3e44a6577fb76bc6ca8bbe (patch) | |
| tree | 9e87a8ff74b470685c9d0a33c7cda8f974766444 /drivers/phy/qualcomm/phy-qcom-qmp.h | |
| parent | 26379667d26f33083484f0df814afec3a955b974 (diff) | |
| download | linux-stable-f199223cb490be108e3e44a6577fb76bc6ca8bbe.tar.gz linux-stable-f199223cb490be108e3e44a6577fb76bc6ca8bbe.tar.bz2 linux-stable-f199223cb490be108e3e44a6577fb76bc6ca8bbe.zip | |
phy: qcom: Introduce new eDP PHY driver
Many recent Qualcomm platforms comes with native DP and eDP support.
This consists of a controller in the MDSS and a QMP-like PHY.
While similar to the well known QMP block, the eDP PHY only has TX lanes
and the programming sequences are slightly different. Rather than
continuing the trend of parameterize the QMP driver to pieces, this
introduces the support as a new driver.
The registration of link and pixel clocks are borrowed from the QMP
driver. The non-DP link frequencies are omitted for now.
The eDP PHY is very similar to the dedicated (non-USB) DP PHY, but only
the prior is supported for now.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20211103234410.1352424-2-bjorn.andersson@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index e15f461065bb..3d123fbe42d2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -551,6 +551,7 @@ /* Only for QMP V4 PHY - QSERDES COM registers */ #define QSERDES_V4_COM_BG_TIMER 0x00c #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 +#define QSERDES_V4_COM_SSC_ADJ_PER1 0x014 #define QSERDES_V4_COM_SSC_PER1 0x01c #define QSERDES_V4_COM_SSC_PER2 0x020 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 |